|
! k0 E% X1 Q. Q/ t, h/ D
寄存器初始化那里就给出来了啊,如果DSP要发数据给FPGA, 那么CLOCK是由DSP去控制的,如果DSP要接收FPGA的数据,则CLOCK是由FPGA控制的,START跟ENABLE信号是用来控制发送使能的。这是我的初始化配置(我是用8位宽度通信的,对于DSP来说,B是发送,A是接收):' m' X1 M& n: y; c( Z' c
static void UPPInit(void)
2 q) W3 I6 }7 \. u6 {{
# P* R% p( \( @' ` unsigned int temp_reg = 0;
/ D. ~" A- {0 s( W! _3 \! o8 d. t+ q( [5 ? x# z
// Channel B params+ R/ F& s5 U9 o% I
CSL_FINST(temp_reg, UPP_UPCTL_DPFB, LJZF); //Left-justified, zero filled9 m& u, J% M; s- e1 ~
CSL_FINST(temp_reg, UPP_UPCTL_IWB, 8BIT); //8-bit interface6 w6 q7 S! Q; H6 M( {2 N
CSL_FINST(temp_reg, UPP_UPCTL_DPWB, FULL); //Channel B bit width = 8! [9 ~+ p; h" V
CSL_FINST(temp_reg, UPP_UPCTL_DRB, SINGLE); //Single data rate
7 `+ f7 e7 P! ^* ]8 ~/ C ]1 O
% i' R e* g: c // Channel A params
a' p- w1 ]2 v CSL_FINST(temp_reg, UPP_UPCTL_DPFA, LJZF); //Left-justified, zero filled8 R$ \0 w$ ?1 A8 }6 u# l0 A
CSL_FINST(temp_reg, UPP_UPCTL_IWA, 8BIT); //8-bit interface0 V; o4 d1 h$ D- v: i& P. X% ^
CSL_FINST(temp_reg, UPP_UPCTL_DPWA, FULL); //Channel A bit width = 8: p& X/ ^1 c6 `/ q# C: o
CSL_FINST(temp_reg, UPP_UPCTL_DRA, SINGLE); //Single data rate
/ A% O; |6 ?: ^( ~6 p2 }
6 s6 ~: l1 ]3 r/ j CSL_FINST(temp_reg, UPP_UPCTL_CHN, TWO); //Channel A and Channel B are both active.# l8 H( W( y* Q2 L! t7 p5 a
CSL_FINST(temp_reg, UPP_UPCTL_MODE, DUPLEX0); //Channel B transmit Channel A receive
$ X c7 C# U( {* @- u# \
% G: U% Q/ Q1 O+ z* g upp_reg_hdl->UPCTL = temp_reg;
5 A6 g0 M6 u" L$ b6 l" y# o% r6 G, n; N+ R
temp_reg = 0; + t3 d" t4 P9 c2 u6 p
" @& c1 a% i# x! [4 b* D // Channel A params
+ `' G2 V% E- X/ w# w; W //CSL_FINST(temp_reg, UPP_UPICR_TRISA, ENABLE); //Channel A data pins are in a high-impedance state while idle4 t$ K" K5 J2 O' d
//CSL_FINS(temp_reg, UPP_UPICR_CLKDIVA, UPP_CLOCK_DIV); //Clock divisor
0 n% i7 R) R* l) o+ O- G CSL_FINST(temp_reg, UPP_UPICR_STARTA, ENABLE); //Channel A START Signal Enable.' N+ M. o# v! m. a. Y+ v
CSL_FINST(temp_reg, UPP_UPICR_ENAA, ENABLE); //Channel A ENABLE Signal Enable
: {" ]( d/ h2 y* _6 K) L2 ~: d! _* c) o2 O0 @: B% ]
// Channel B params
' M* n6 x2 A7 S3 D" o/ X CSL_FINS(temp_reg, UPP_UPICR_CLKDIVB, UPP_CLOCK_DIV);
# z( W, h7 B$ O6 o4 _, s CSL_FINST(temp_reg, UPP_UPICR_STARTB, ENABLE); //Channel B START Signal Enable.
4 l3 S2 E3 j7 F- O) e# x# }% p5 k CSL_FINST(temp_reg, UPP_UPICR_ENAB, ENABLE); //Channel B ENABLE Signal Enable, g) h- j1 ]/ ]) z- {
" O: F) B! z H2 N3 F- s upp_reg_hdl->UPICR = temp_reg;% X. u8 X- }, m/ Y
2 M& D3 j& Y- F; V/ u, r5 R0 [
//temp_reg = 0;
6 @% _ H/ R6 q9 T3 O* h' k) o& F( f/ \9 N
//CSL_FINS(temp_reg, UPP_UPIVR_VALB, 0x7b7b); //Channel B idle value7 f- v& @4 ]; @3 `7 F( {
//CSL_FINS(temp_reg, UPP_UPIVR_VALA, 0x7f7f); //Channel A idle value
, j( W n( m: c7 b1 f. c* P, {+ I+ F7 Z
//upp_reg_hdl->UPIVR = temp_reg;
, c2 Z2 o' f, L$ O! F2 Y9 `
: q, D! P3 J | //temp_reg = 0;
1 @! [" b [$ e& d; U1 ?6 X4 K7 U' p O; S8 r+ K
//CSL_FINST(temp_reg, UPP_UPTCR_RDSIZEI, 256B); //set 256B DMA I
0 R! J/ g& G1 ?% F, U" o2 k+ c" h //upp_reg_hdl->UPTCR = temp_reg;/ S0 x3 ^0 h, [$ k
& Y' u* q9 m6 Y //temp_reg = 0;/ h" K; H) R/ l6 l6 I
//CSL_FINST(temp_reg, UPP_UPDLB_BA, ENABLE); //B to A loopback mode enable
) w& b9 W; g5 `3 z& P4 i$ C //upp_reg_hdl->UPDLB = temp_reg;
$ T/ Y- S1 |5 q" Y# i( T
1 O2 h& x/ b0 `" ^3 N, K9 _6 ~} |
|