我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) x/ U8 |8 C. w* D `input mcasp_ahclkx,
+ Y. }0 V! Z6 k; ]; j6 o4 @input mcasp_aclkx,
( ~' y, w9 {' T4 s3 L. o, jinput axr0,$ o* ~; A5 `4 F X8 t
2 r) D9 ^8 b1 U$ \" G
output mcasp_afsr,
0 F, Z5 b1 T/ n# ^8 a. zoutput mcasp_ahclkr,
5 b% O) Y% S5 joutput mcasp_aclkr,( L. g$ F6 {! U1 f" Q3 L% p' m
output axr1,; O* F* g2 L4 f! W0 N, s
assign mcasp_afsr = mcasp_afsx;
/ |# ]( A- D! U0 H/ e- Fassign mcasp_aclkr = mcasp_aclkx;) Y0 M j# u2 i7 g8 L; K) n
assign mcasp_ahclkr = mcasp_ahclkx;* c# |) N4 S1 X) n/ F# R9 O
assign axr1 = axr0; 6 J1 u: [! T& y3 q/ y4 V# O
. c! V' y% t* B. T) f+ B, A* j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , _) T- x& h$ y$ I
static void McASPI2SConfigure(void)
% I5 |. A3 N1 T9 @5 f{2 X V* l% N0 a& f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. k5 F5 A- j" @9 w& E: b o* L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 b3 i" F8 q1 s5 v/ @& K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& B2 r4 O; V0 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& B* l! r3 r b0 A7 a, F& S; aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ?) d3 v3 j- y, {MCASP_RX_MODE_DMA);. ~% a, C7 ?* S) G1 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 m4 {' `2 z, o5 U6 S0 P; m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ F; |6 w2 y5 Q4 x3 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 w' C/ }' x+ P# g/ H1 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" e. s, A4 l' U# L8 T8 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) q* k3 X# w$ ^" c m, ~1 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, B1 t6 s: Z2 P9 B% V& r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: ~. V2 Y7 D3 t; f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * n0 G8 H w2 S& o/ G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, O2 L, f% J/ c2 K
0x00, 0xFF); /* configure the clock for transmitter */
4 I' j; W0 A. I. ]% r! Y; P, Q, LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" ]/ m' d3 R8 f; D4 K, ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! K1 R$ @( D% ^0 s8 x+ Y; D: lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ [0 C" Q, [/ a) A
0x00, 0xFF);
7 g" `0 c: `( [, U8 W! K9 L' r" A. b: N* n" U
/* Enable synchronization of RX and TX sections */
2 o. _# v+ P/ u! K/ G* c( vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 \, O' v/ b* [" x) n% T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ O1 y% x t) |, ]1 i% f* d' LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ s7 u9 v; R& c9 B( h0 _4 J** Set the serializers, Currently only one serializer is set as
) ?* D, m% ^* z. T) m3 J& Z- x** transmitter and one serializer as receiver.; `) \ M' s2 U& E: ~6 {+ `
*/8 k" a: d7 v [2 S; \& F6 u, T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ e/ c. g, e4 K: i* Z+ j5 ~# Y2 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 \- k l- a4 x2 o: j4 k** Configure the McASP pins
) [- g" ^2 x! B% k2 X** Input - Frame Sync, Clock and Serializer Rx
" O' n( s% { F1 W/ ]$ F7 v8 R** Output - Serializer Tx is connected to the input of the codec
( C" g( j: w! {*/
B) z4 P$ [! |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' U$ c+ O! }, c- [8 N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( A3 q* V6 G, l* D* mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* g0 L1 h. N" Q! W1 Q| MCASP_PIN_ACLKX
, `' k/ c7 e9 Z4 y| MCASP_PIN_AHCLKX
s2 X7 S" R$ n- } d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ A: S, K0 _! ?% X3 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 S( D# } Q+ u( \| MCASP_TX_CLKFAIL
9 o% `% Y& {( ~| MCASP_TX_SYNCERROR
; a' N/ a. I1 E% W4 {3 b; z* R# H" W3 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! }0 [6 w* G% z4 U/ C| MCASP_RX_CLKFAIL
+ ~* H& H6 W3 E* s0 I- P| MCASP_RX_SYNCERROR
% j( ]- \$ d2 B. e4 R4 @| MCASP_RX_OVERRUN);1 j8 Q7 u. V8 r1 ]0 M* X: x
} static void I2SDataTxRxActivate(void); d F- j6 ]1 Q& ]4 u
{
- F- A5 `/ Y4 o/* Start the clocks */
' }. g- \4 T# ~" z9 B: kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 j% E. K+ h7 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& W& i8 ^$ W `. }1 A2 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: B S: I, n' ~
EDMA3_TRIG_MODE_EVENT);
' d+ z) r$ {8 N4 u. c: G6 i% oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) A4 W- v! i7 w* ^2 E$ k6 \6 f4 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 ~9 h- K1 L+ e' I! w& jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ B9 ^- e* G1 }! Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: W0 v1 }* O+ h* f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 f, d5 D7 D& K$ a8 V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) B) O9 e5 t* ^4 L5 k# O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- q3 S: u, I) R7 E- Y( e! P8 p}
$ k) }1 n, l C Q4 E8 W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) ~' p' B- a* o3 V2 _
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