我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! {* p7 P: p1 G8 C! Sinput mcasp_ahclkx,
5 n( \6 q2 p$ i2 Dinput mcasp_aclkx,- p& }* Y4 _+ P7 A
input axr0,/ p. F' `) S; X6 x$ ~6 r$ r
+ s1 `" k% H% E# r' R
output mcasp_afsr,
+ [4 v+ s" j2 v7 [" S! Woutput mcasp_ahclkr,( A( K) W$ [( F, {
output mcasp_aclkr,
1 C5 Y/ a3 z0 F2 toutput axr1,+ r7 s2 q. I0 H2 L
assign mcasp_afsr = mcasp_afsx;
5 ]) W* c; ^% h5 j0 zassign mcasp_aclkr = mcasp_aclkx;
$ A' S+ V! n, Y; ~4 u9 Y: ?; zassign mcasp_ahclkr = mcasp_ahclkx;
# i: C; I0 X4 b9 m5 N4 W* aassign axr1 = axr0;
c C* W6 k2 G( s
& c, l3 V# M& O, u3 z. x& m# j" \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 r( R$ L* ?7 f& I5 {5 Z4 @static void McASPI2SConfigure(void)
' f; M1 ]# D+ ^4 e" x% j{
$ [" P+ R$ c/ E! `# b# ~. jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 C5 i( q8 t. ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" B" {. E; j1 Y z/ c7 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. I+ ]' X* z$ j) J C" e \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ {5 r3 H% \$ i4 d! q, L8 P1 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% R3 m3 d4 S6 z5 C5 VMCASP_RX_MODE_DMA);' L, \$ a9 W7 u; O0 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! W9 b& A4 m7 z1 Y* M6 n4 A2 T8 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ t3 p7 [# l0 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: n8 n6 @) w6 I) V bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 n: e) q2 U! ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ U# Q8 h+ z: R3 h6 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 X! `! N- j2 q! w/ ~$ kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* Y) l3 ?* q7 l6 M* l3 y& @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & n+ A9 v9 p6 P$ D$ g' g$ L5 q+ N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% [ F- m4 b5 k- o! c) v3 z
0x00, 0xFF); /* configure the clock for transmitter *// a5 ~" t% F# o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* A+ A- \; `. bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' @. T8 @/ B8 B( @) M" V/ q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* Z: |3 s! a' X4 D( B3 N
0x00, 0xFF);7 z" n% @6 [0 n6 q; c
; f5 v0 w2 d8 R7 N/* Enable synchronization of RX and TX sections */
+ Q' C0 e9 N" N7 o" `6 C2 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ ^7 {1 g2 c& Q& x* G% J( Z" nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& s7 A. T$ ^- e, f6 V2 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 \# D1 L$ E. A, _** Set the serializers, Currently only one serializer is set as
# R/ @4 S, F; ]8 x: y** transmitter and one serializer as receiver.( x% E! m5 M6 R& s G! j
*/: h4 N0 J$ a+ u6 s) I0 Z' }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) q' d; J$ n/ k5 E; o$ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ x* ?; d, {$ q% S# b4 N; N** Configure the McASP pins % z4 A. q$ d- X+ ] q
** Input - Frame Sync, Clock and Serializer Rx' l9 |0 m) [' y& ^8 d5 G8 R" [
** Output - Serializer Tx is connected to the input of the codec
- n# d* h* O1 i9 Y4 b' p: @*/# X3 k- t/ N5 |4 F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 ~+ G) K9 n' A. t4 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: H7 b$ {! I& c2 Y* I3 L( M% {) G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# t9 p3 M- H( A6 @! w4 p/ [5 U| MCASP_PIN_ACLKX
. |/ V& F0 @. D, k' [" M| MCASP_PIN_AHCLKX
; L8 A+ R! A, F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& x$ E; s; Z) s9 I; l9 y' p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ Z* K7 @8 A' K| MCASP_TX_CLKFAIL # ~& F2 u2 T$ ]* Z( d( ]
| MCASP_TX_SYNCERROR; }% d' Y, s$ f$ J$ w. D% N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 y/ k0 U5 n O0 A
| MCASP_RX_CLKFAIL+ D. F1 Z2 V2 ]5 r6 M
| MCASP_RX_SYNCERROR - j0 P2 k9 Z9 R3 ?/ w4 J
| MCASP_RX_OVERRUN);- f% r/ ~- t, \ p
} static void I2SDataTxRxActivate(void)- z0 r* N% [' y1 Z( h$ E
{, {- c; v3 h5 v9 v
/* Start the clocks */2 F5 h. x) L8 m, E) D: S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 q& {" z, @2 z$ Y! mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 m0 n' S# Z% J0 L+ O2 E; R4 R3 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 j( a, j$ q) W# J) |. V5 cEDMA3_TRIG_MODE_EVENT);/ v0 r' o' C) b' Q/ o: Y% F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % x1 }6 i' N# a3 m l3 F7 K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// s0 [" S: @3 j: h2 B9 L: |5 C: G1 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 ?3 T& f, A& U4 I$ z4 |3 J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! v! ]0 {6 _! K# T F' l/ s% g8 C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# ]; i5 e, f3 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 q% v$ ~# F( ]$ ~- U9 v" wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) |3 h5 O$ p* j0 ~6 X}
3 t2 r6 E2 `: F( g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
U1 D) {% d8 M8 _% V |