|
我的McASP配置分别如下:
# E" P) _/ D, Z1 _管脚的复用设置是:- e6 A+ y2 |7 m- f5 z2 t7 g
void McASPPinMuxSetup(void)+ p7 D1 C! Z q$ p
{
- ~, S4 r" U2 G+ M unsigned int savePinMux = 0;
5 w" _! c8 ]8 h savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
1 ]8 J/ ^2 O* N) Z$ K ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
r" [- M0 a c7 O u! a SYSCFG_PINMUX0_PINMUX0_23_20 | \
& C V) n9 n% x SYSCFG_PINMUX0_PINMUX0_19_16 | \* Q* b1 T$ r k0 S1 o
SYSCFG_PINMUX0_PINMUX0_15_12 | \
. P* E0 T% O" L* g SYSCFG_PINMUX0_PINMUX0_11_8 | \/ c" S# O, h+ S8 @& B
SYSCFG_PINMUX0_PINMUX0_7_4 | \
% Q$ e+ T2 U& @1 \$ W* w& ? SYSCFG_PINMUX0_PINMUX0_3_0);
9 u: C( Q2 x* e! e* ` HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
8 k' ?: ]3 Q8 t2 O; z$ U (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
0 X' r9 p t4 a, l; r: t) K& B PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \8 O& d. I8 f4 i4 W0 r2 Z& T6 n
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \* j3 n1 U0 w+ g: T8 r: d
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);# Y, A) }/ R& h+ l
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
% ?% R) f- O$ o" e ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
G$ a" d7 N( D7 {8 f/ v( s SYSCFG_PINMUX1_PINMUX1_15_12 | \
8 [1 h, h8 h. ~& | SYSCFG_PINMUX1_PINMUX1_11_8 | \
% J+ A. s9 r$ ~; x" k1 G+ _: C SYSCFG_PINMUX1_PINMUX1_7_4 | \0 R, k. Q1 ^0 z- ^. G2 K8 M0 o7 f: I4 I
SYSCFG_PINMUX1_PINMUX1_23_20 | \( r# k6 Z5 ~" j: G; J& i7 |, a
SYSCFG_PINMUX1_PINMUX1_27_24 | \' R5 A+ S8 B! W+ n+ C
SYSCFG_PINMUX1_PINMUX1_31_28/ ]& D' p7 w, K: S( l
);; e$ O8 M6 e% X0 ^5 [# _0 [
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
( g1 j) _ K4 P( n' f C$ k* g (PINMUX1_MCASP0_AXR11_ENABLE | \+ g( e6 c8 o1 u* Y/ i
PINMUX1_MCASP0_AXR12_ENABLE | \6 c0 H( i& r, o5 h
PINMUX1_MCASP0_AXR13_ENABLE | \
8 B* L" g8 t# M" C7 Y PINMUX1_MCASP0_AXR14_ENABLE | \
5 U6 B6 U1 ~8 I X8 M. _5 f PINMUX1_MCASP0_AXR8_ENABLE | \
5 B7 Y, q5 J3 a! k6 _+ G PINMUX1_MCASP0_AXR9_ENABLE | \( u! @. g7 B, m' Z
PINMUX1_MCASP0_AXR10_ENABLE | \
5 E2 q# r6 P" h1 m7 c- ?7 ~ savePinMux);
: X- r# @* x- ~, R m8 q}
- Q4 X" X% B: b! n2 I% v F. u" U7 m. z( ]9 O
1.McASPI2SConfigure(); McASP的配置程序如下:) k" s" O. {- Y8 s" s
static void McASPI2SConfigure(void)( S& K4 V, S- c [1 ~2 K" K& ^
{) v9 O0 R% ]9 T$ Z; q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 c2 Y6 S* |2 u; W5 U McASPTxReset(SOC_MCASP_0_CTRL_REGS);
: A" {' O9 P# `3 J6 q
! [; g- z# Y' G /* Enable the FIFOs for DMA transfer */0 i- R; {8 X4 i. \$ S" O* h
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
+ D" \- q- v ]1 t1 f2 ^// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* u- _1 R& R' f7 A% a
4 y# U; i+ w( P. q1 U- F8 Q /* Set I2S format in the transmitter/receiver format units */
# g, I; n3 F* L9 D3 J4 F McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: ] {2 a' s% O! F) L* L
MCASP_RX_MODE_NON_DMA);
/ r+ ?" ]1 k* ~/ F McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 S+ A3 D x- \
MCASP_TX_MODE_NON_DMA);2 T6 ?0 y. B8 S/ l% f6 E
' Q2 M8 o" E8 \9 x! j3 E /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% f: }( ~ V7 h" k# z' C. _& K+ g9 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 ?/ b& a3 {- T1 X7 ^+ g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ w4 ~! I( x D+ o McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 Q+ k7 z$ [5 C7 G MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
! M$ S9 X+ Y4 b+ n, a! _* e, b+ J- a9 D. c4 A) ^1 c. ^
/* configure the clock for receiver */! l! j0 u& x' o! F* w
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);! o' V$ W% h; d! m) a: {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 Z8 ~+ C; z/ q, C0 R& _* t/ N+ B& M3 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);! C7 s, I; ?! g" } D2 k c- _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# a' K9 O9 u0 `2 t 0x00, 0xFF);- |$ x& K, `; U8 Y7 c% e; f
7 N) y( R' ]9 D7 k
/* configure the clock for transmitter */7 l2 y5 V2 N2 E/ U1 q# t) @1 x/ E
// HWREG(0x01D000A0) = (0x00001F00);
- G+ t8 F( [* m0 y2 f) c: F// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
- X4 D: U3 {8 U McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);6 B# Y0 ]% `) a% s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);! U4 J* V# z+ ?/ e" P: r, Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( y; ^! A! T* {$ R( U6 v) x# t 0x00, 0xFF);, X8 z* \: k. v- C" F6 E6 F
$ h% _5 B/ K& x4 a) d5 l0 } /* Enable synchronization of RX and TX sections */ - S0 ~/ e7 ]# I+ ?& r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);0 I4 G# E. g; m6 P4 ^1 s6 e, G
; [# A9 c! j# j /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 j* ?- y0 c7 a3 b2 k, i McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 R. S7 P {2 n3 `; G* c ?5 U! n3 [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 D E% D& r3 B: G6 z
M% L6 u: P4 C' l1 u9 \! z /*
: }1 Z- J9 w7 T* [: `4 s ** Set the serializers, Currently only one serializer is set as
/ y! i% t. f2 }8 z5 B; v$ Y; ]! Y, P/ k ** transmitter and one serializer as receiver.
7 x3 {( U/ ]" n9 S1 A, T& S */, Q# i) J D& x- C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 m) G! ^; a2 b7 d* y- Z McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
8 p6 A `) p2 s" y _% t McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);( ?: o- U% Y. s0 |; w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);! o+ Q' N: u0 t# {8 Y1 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
9 g3 w8 a& ]) O McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
) T( C% v3 E: S& E$ F; W
0 k/ B% U" E7 V3 K t McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
) R% o# r! b/ {' O- i0 a5 R+ g% J' X* Z* \) m9 w
/*
1 s# Y. \# M9 {! g) H& j ** Configure the McASP pins 3 f, E4 v" E. P- [
** Input - Frame Sync, Clock and Serializer Rx
. }& L& h1 F; i; R7 \ ** Output - Serializer Tx is connected to the input of the codec
" J0 k6 g( v- D7 H */
' E9 P0 K% N& N2 D4 M& ?1 C4 b McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 v8 l7 h- s) R5 `1 \$ y, D! b0 ?( g McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,( \- G+ s* h: [% `( F4 B) _$ a$ T
MCASP_PIN_AXR(MCASP_XSER_TX)/ V7 c# B- g6 F' }8 X/ K. d& X# q
| MCASP_PIN_AMUTE
- i. ]- }- \4 S8 j2 R );
4 z9 \) a( Q- T/ s% X8 B7 p McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,9 O! V3 W, I2 D. t$ Y" i, P
MCASP_PIN_AFSX
. C7 Q7 U2 n1 e1 y" y' X! x | MCASP_PIN_AFSR
$ p8 B d* t2 ?# E | MCASP_PIN_AHCLKX
- ?" i( m- h Q- I8 ~/ v' \- A | MCASP_PIN_AHCLKR2 G2 _0 G) t" f# n+ m
| MCASP_PIN_ACLKX0 j% c5 k# {5 p$ G* F) v% Z0 n
| MCASP_PIN_ACLKR( P) A# a/ m7 ~) K; `8 b
| MCASP_PIN_AXR(MCASP_XSER_RX)5 c: X3 D* X9 j( ~+ ^
| MCASP_PIN_AXR(1u<<(13u))
' c7 O( E& s* v; i | MCASP_PIN_AXR(1u<<(14u))' T% t/ j8 G8 N _, a4 E& l
| MCASP_PIN_AXR(1u<<(8u))
0 L: L5 g8 J: T | MCASP_PIN_AXR(1u<<(10u))& X- E8 v$ x9 }! J
| MCASP_PIN_AXR(1u<<(11u))
4 G i+ j4 b2 _: t! j k );
7 z3 [9 g2 I- z8 g& L2 p" L# y1 V% t' G6 u1 M, W0 Z3 K5 K; \
/* Enable error interrupts for McASP */
' x% |; x9 U: c; Q! q McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,! h- q& q: W: M* l, D F2 e# J g
MCASP_TX_DATAREADY, S9 E* o& @6 R) h- s- o
| MCASP_TX_CLKFAIL
+ [! ?! w, Q }' b& B | MCASP_TX_SYNCERROR; q* J2 q/ S, E& u( |
| MCASP_TX_UNDERRUN);9 \/ ]' ]& M$ Z$ E: Y
g9 a4 h% O' [$ z f g McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,, j' J m q" U1 m
MCASP_RX_DATAREADY
- U1 K3 ~( [1 _# L, B% y. z | MCASP_RX_CLKFAIL5 [" W9 U* R ^; t6 c: A
| MCASP_RX_SYNCERROR ) e: r# C% U% Z) r
| MCASP_RX_OVERRUN);
: J }/ _$ c0 Z& I//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
" U( s, p# A7 H! J) D% A" [
* }2 k5 a+ v* |1 }( E: S$ N4 I9 G) p}: B8 k4 l1 k( Z9 A) b3 q' F+ e
) R1 A; @" U- l" S2 b5 H2 R2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
' h3 n$ {! s# R4 \/ j2 _! Rstatic void I2SDataTxRxActivate(void)
8 M& ^3 h/ J! ^$ i0 j3 o{ |5 f+ ~# [; A* ?6 X
/* Start the clocks */5 O( F7 w9 b# T: c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, K$ w* h4 p, b5 C5 E7 v Y' ] McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
{/ V2 O4 W+ u* {2 k7 |) @( ?' X5 B1 }9 W7 T
/* Enable EDMA for the transfer */
. F0 V! X, V! i, W// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 S+ n5 g0 s+ W5 d// EDMA3_TRIG_MODE_EVENT);" v( C0 [* n; ^3 Y8 \; Q2 b- `' Z
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,0 e$ N' z% L. g8 `% a% x. L
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
; C" h8 L( k- ?' E+ S /* Activate the serializers */, t! r* W1 G/ p7 \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 [ m6 C; Y: g3 m+ L& l McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);* P7 Q- R p+ Q$ C* x, O
/* make sure that the XDATA bit is cleared to zero */1 s5 L2 ?9 p" Y0 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/ w( w5 s+ Y" G7 v( N /* Activate the state machines */
- p" T6 |% B3 {# x3 C0 I McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ l3 n" \. H0 _# U* w McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% e! |$ F$ J; n% ? \$ M7 r+ m5 w McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
4 O3 K, o5 y% @; F7 D2 d: h}5 n q8 D7 V* Y7 k8 G/ n
5 \0 D- P) ?. _7 R |
|