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我的McASP配置分别如下:+ V. ] V- Z7 j/ m' l c5 O# A
管脚的复用设置是:
! u) V! P$ c# x+ r1 E+ R) u$ Zvoid McASPPinMuxSetup(void)- E+ {6 D6 c3 M; K o& @# q
{. O) V9 s3 a- _* S6 Z2 z8 X
unsigned int savePinMux = 0;
5 L1 g3 T! S. J5 R0 k- C: u* g savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
( S; e( D, L8 Z a7 ~1 i. } ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \1 Z% h" |: r+ @6 \! n' O
SYSCFG_PINMUX0_PINMUX0_23_20 | \, Q+ _0 Y3 w$ f Y: ^
SYSCFG_PINMUX0_PINMUX0_19_16 | \
9 a6 O* ?! R E, u7 e/ b6 A SYSCFG_PINMUX0_PINMUX0_15_12 | \( a8 x+ M ?9 p! ?0 x/ J. i, a
SYSCFG_PINMUX0_PINMUX0_11_8 | \
6 D. X" L% [( `" j SYSCFG_PINMUX0_PINMUX0_7_4 | \
# s+ _( u$ c0 m; Z7 O: a/ D% R9 j SYSCFG_PINMUX0_PINMUX0_3_0); t1 }. J1 u" X1 m! ^1 n
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \$ T S0 K' f+ N8 r& U/ f8 T; n6 @
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \- o9 s. K. L/ o7 r5 `, ]+ d
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
5 g4 h( v$ M* a5 a: s PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \" D" T- K' J( j( Y1 ?2 w
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
: s' o6 z- Q8 Y( i savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \6 O; y* z1 g0 p1 W
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \# }3 `6 M; X- F9 \8 n# V
SYSCFG_PINMUX1_PINMUX1_15_12 | \
/ F8 X# ]5 W1 r4 Z, l- h" { SYSCFG_PINMUX1_PINMUX1_11_8 | \
* L }) O* A9 J0 r( I SYSCFG_PINMUX1_PINMUX1_7_4 | \
3 o4 h3 C$ u8 l$ S SYSCFG_PINMUX1_PINMUX1_23_20 | \
6 p, |. e o! i SYSCFG_PINMUX1_PINMUX1_27_24 | \
: o4 h ?) Z/ [3 n+ e5 U SYSCFG_PINMUX1_PINMUX1_31_28# A% E2 t0 Y& K! v b: t
);
3 X" {" d: [) {7 t a9 f HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \ F* y, V' d) f" l
(PINMUX1_MCASP0_AXR11_ENABLE | \
5 Y4 T4 s5 l3 D; b/ b4 F6 { PINMUX1_MCASP0_AXR12_ENABLE | \
9 J8 Z S9 R0 W1 p9 J PINMUX1_MCASP0_AXR13_ENABLE | \
0 G1 e. P1 }1 C! X3 Q5 K, F& T PINMUX1_MCASP0_AXR14_ENABLE | \# f& W$ O [9 j1 q) ? q4 m
PINMUX1_MCASP0_AXR8_ENABLE | \4 B5 q; L3 G8 l0 K
PINMUX1_MCASP0_AXR9_ENABLE | \
& O% T' C* F- h" i PINMUX1_MCASP0_AXR10_ENABLE | \
3 h, B" M8 m' {7 a9 o savePinMux);5 y7 b4 d) C- b0 _
}# y6 d. j$ z: ^1 m& z, y/ N
6 ~1 ^6 w) H9 r+ h+ X
1.McASPI2SConfigure(); McASP的配置程序如下:
# B6 `4 y( T8 Tstatic void McASPI2SConfigure(void)8 O+ O. d1 h8 G& b9 d& o5 n3 }% Z
{
9 U" n* W/ e5 n! t& H8 W4 {4 M' u McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 |0 t0 k4 C5 G1 P; Q% U McASPTxReset(SOC_MCASP_0_CTRL_REGS);
! {6 \6 j! k) Z% T) U3 ?, V' C5 ?' l3 Y% X1 m1 k7 V
/* Enable the FIFOs for DMA transfer */
9 R1 h5 O; `2 _" b// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);+ G `( h2 w# S0 L
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ i, h0 c' S$ ?; C( }2 b6 }" d/ S2 X* l# H! ^
/* Set I2S format in the transmitter/receiver format units */
# n4 T7 L n4 Q3 ? McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 R: o# K0 s# H) v
MCASP_RX_MODE_NON_DMA);' L0 A, H1 R# o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* M; b0 i9 f% M& n: a MCASP_TX_MODE_NON_DMA);4 y) [( |2 k9 i
; T0 m. U7 v0 x6 u
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' a8 Q8 s, w& {3 a" W McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 W0 X/ j1 w4 H. N2 N- B; F: n# ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
?/ }2 o% F- q9 w* b McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + k) @# d& O* W" Z/ [. ]
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
$ ^: l8 c' q, f& Z: n. `5 t# z4 R8 q; x; E
/* configure the clock for receiver */
' R& w3 t. l" p; p! y+ {1 _6 m0 b// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);8 b+ V9 k) i8 j6 I5 Q7 h) ?* W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 ~9 I1 ]; D4 V; p( v: ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' }, d1 e- a5 ~ X( O3 ?! g+ d McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 t) ]# O! u2 W& K
0x00, 0xFF);
4 d" Q: ?, i6 L( M) w* [; _
9 D1 I }6 L; Y5 i0 q /* configure the clock for transmitter */
$ ~, G. S+ m; H9 Z7 g// HWREG(0x01D000A0) = (0x00001F00);5 I: m) ~1 M( O0 i& y' B
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);; m* @: i. k2 u8 u" J! E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);- l6 W* \& [7 E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( o0 d3 V5 N4 t/ h McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" _8 z5 D+ P" F q" R 0x00, 0xFF); y# c( {& m, E9 ]" ]7 r* {2 G
1 Z4 ?; D% d0 r; W7 b) ^4 E
/* Enable synchronization of RX and TX sections */
5 x7 T+ [- _6 w6 d" W2 I McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);. G- Y! C; m; o# Y0 r2 ~- Q
! q: g! @: I1 L. q8 R7 x$ Y /* Enable the transmitter/receiver slots. I2S uses 2 slots */& O% ?, @1 H- T3 G2 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 a$ s0 P, A8 g/ c6 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& s/ u1 v+ ~2 k" d& r! |
+ w: L5 F9 Q w9 K, O3 m /*
! {# d9 ^: p, z/ b0 R ** Set the serializers, Currently only one serializer is set as
3 O. z% ]* R" q- P/ ~ ** transmitter and one serializer as receiver.+ L4 r: ?; w+ {9 `; T
*/
; P+ Y) ^) ^$ l McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ u9 j# q$ p0 q; r McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
4 h% U6 G+ ]+ L; N M4 X McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);& S/ y- h" h% @1 t" I" r6 x$ u' V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);6 v- V+ ]7 r/ H8 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);+ P4 g# {" `* x0 ~/ A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);5 P, B$ z& t2 [- s
- \. J( q, C' v% U7 @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
8 S1 c* V; P" b* Z/ @$ T# r+ w" N7 [0 f4 L" k: r6 u# z
/*
0 T# B6 D5 M- O3 I7 M) K/ w% D ** Configure the McASP pins / r/ N, H7 |& q. e5 D. {: Z& I8 g
** Input - Frame Sync, Clock and Serializer Rx7 O" e0 i, R( L: V
** Output - Serializer Tx is connected to the input of the codec 3 | P! V2 S1 v$ Y* N6 C8 T. P$ Y4 x/ \
*/' L* R, x% U9 |+ m K, Q' r* k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ X+ T& J. p1 r9 t7 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
+ u0 o* k9 C: c0 ?! b% o- o MCASP_PIN_AXR(MCASP_XSER_TX)6 k) O* G9 O. T# K3 A* w3 a
| MCASP_PIN_AMUTE
7 \3 N7 c F( F% K: b3 a% i );0 _+ m9 {, l% M$ M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
]& m: o! P0 Y8 V3 W MCASP_PIN_AFSX; J' b k- m! n# L! j
| MCASP_PIN_AFSR) R9 t8 v0 a L
| MCASP_PIN_AHCLKX
* `! u& g( x4 F* O | MCASP_PIN_AHCLKR
4 n; g, x) V0 ^# Y" e* O | MCASP_PIN_ACLKX
: j1 {0 Z2 C* m8 i* [' I9 e0 L, g | MCASP_PIN_ACLKR
! C4 N( t# ]2 ]& c- ?& p9 e | MCASP_PIN_AXR(MCASP_XSER_RX)9 K' ~9 p7 J* Q
| MCASP_PIN_AXR(1u<<(13u))
. \( P/ X( @1 x# J | MCASP_PIN_AXR(1u<<(14u))( x9 f1 P+ N! x& q* c/ J. z) Q
| MCASP_PIN_AXR(1u<<(8u))
, ~7 Y" [( q- f2 ?+ ^8 | | MCASP_PIN_AXR(1u<<(10u))
0 a ^+ Q6 E/ d$ ~ | MCASP_PIN_AXR(1u<<(11u))
$ @% `4 n' B( x8 r4 B );
4 K+ N" H: z% s& A, H" w$ S H. ~! }1 L F) Q9 k
/* Enable error interrupts for McASP */2 m3 n9 ~! ~/ N' b6 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,% J& u, s2 d; U/ G6 e8 U$ h0 }
MCASP_TX_DATAREADY
" _( h' Z; ^! x& P | MCASP_TX_CLKFAIL
l4 Z3 o$ O: s: ?% A" | | MCASP_TX_SYNCERROR1 A) s% z1 S- }8 v' H
| MCASP_TX_UNDERRUN);/ z' a# A4 N7 ]9 v! a D7 n
: D( J5 J! H+ ?" V6 i% K McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
6 b2 q& u0 L w# H9 w MCASP_RX_DATAREADY5 J) [( \ h/ U6 G- M, T
| MCASP_RX_CLKFAIL' I9 f+ {3 R: k3 L0 j! T
| MCASP_RX_SYNCERROR
( W% T9 u4 U% T1 Y8 l7 h% z( ~ | MCASP_RX_OVERRUN);
% I4 e# @& S5 e4 d S, L//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
, ^1 l, H& C) m) |3 Q a5 _, P, l5 U; `1 }
}
+ R1 u, b H. T: V! f$ J! O4 S: K7 a, J6 q& L
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
; Q5 l% P8 O: b* ]/ V/ n& ]4 Hstatic void I2SDataTxRxActivate(void)
3 G7 {; _' L/ Q/ @( Z( O{4 A# K$ K0 x' Z
/* Start the clocks */
8 \' M/ ]: ^/ \. Z McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 K A# H7 {* E6 a" e/ U McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
4 `# R7 ^5 \4 p' r$ L4 y( c( W7 K1 x; c* u7 _5 c
/* Enable EDMA for the transfer */9 ~1 l- K9 U2 _; X0 b6 |: p1 _+ N
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 E a3 s2 Z3 r0 I, E6 `
// EDMA3_TRIG_MODE_EVENT);
5 u! B6 i8 V5 ] J# b7 o// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,* }9 C+ c' E5 ?: [" F# ~* }
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);+ g" K2 F& c5 C3 m. k3 ?; M
/* Activate the serializers */
6 [! g0 l# @$ ], M$ Y' e McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! H0 g7 P% f5 L* R6 j: B McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
! q3 W, w+ m0 |) j; N /* make sure that the XDATA bit is cleared to zero */
- J7 R0 W4 c: i; B6 Z while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
- T2 c" Z/ Q- e /* Activate the state machines */
6 A! h$ l6 L9 d# k0 \1 G' T* _5 ^ McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! [( k1 U+ V' t1 E6 j: g McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# \/ f) l- E3 W, d
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);2 |# Q7 F' U) d+ n0 l0 K% }, j
}' g4 T6 U: W ?0 t2 v
( l p( ^( z: W* ~ |
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