我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& q) D+ ]+ @$ J; x3 Z) hinput mcasp_ahclkx,, c P2 h" B' N) C4 L
input mcasp_aclkx,
9 d: i: f% {8 ~; U( A% Finput axr0,; t w! _6 R. K+ F' ]8 K5 e
/ t) P4 H) Q5 w5 t1 e3 k; \1 {output mcasp_afsr, t+ @7 r5 ]% Y3 f
output mcasp_ahclkr,' |6 m% B$ q; a- e4 ~% B6 n
output mcasp_aclkr,/ a. F& U2 t! }% P/ C& `1 T% |
output axr1,
' u* b, g$ Z. [1 p assign mcasp_afsr = mcasp_afsx;
& ]# Q1 U( t9 jassign mcasp_aclkr = mcasp_aclkx; C" K! l. u6 d' v, x# n6 ]- \
assign mcasp_ahclkr = mcasp_ahclkx;
2 H, y2 x2 P9 ~" rassign axr1 = axr0; l+ M, I' J- |, |: Q
+ e- |+ `3 }; u% K4 B9 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 z+ U& E; U2 F4 U: r U
static void McASPI2SConfigure(void)
& ?: s; I/ H/ ?6 ?! f{
% r: I; \& F+ F; _7 Y) ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* E- @, F: O8 X& w# O& B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ k) q; O3 [- [7 ]1 B; C. cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ @0 w6 ?: e1 o- q0 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 f( c) p5 J4 B0 q) U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% j) z; s! Q2 Q3 i" N/ P
MCASP_RX_MODE_DMA);
D: A- I3 {$ H J7 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 l8 M8 V/ m8 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! I: b( z5 v0 _8 m0 e1 _5 N8 h( `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( c' m0 E' y; Y: d4 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ X+ N3 i& o8 v6 A0 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 q8 Q; J' u3 t6 C' ~ c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 N. m k8 x- |! b0 }1 M" h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) e8 Y* W, B Y# j7 o f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 s u( f' A& g$ _" S2 O! cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 w* j2 D& F1 q t! x4 L, B- w
0x00, 0xFF); /* configure the clock for transmitter */1 ^$ t5 q) y" i7 W" J# X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* u3 H2 `0 m4 F: n6 V+ ~3 I* P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + ?+ ?7 ?/ n" `/ k% D( M& t0 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 G+ p6 }) v7 b6 T5 A0x00, 0xFF);
1 Y( K8 }" G, j+ }, f" ?: m6 z
$ U/ ]* F3 O; l/* Enable synchronization of RX and TX sections */ , Z2 C) L" x6 H ?4 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 d8 V6 [; \' j( B* R% x. ]% uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 u8 \. d8 J1 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, {' V$ o5 U: p9 `& D, k** Set the serializers, Currently only one serializer is set as
5 c3 ^* O+ k6 V9 }& Z6 A** transmitter and one serializer as receiver.
* ?/ \# H- T) _! R# r4 x0 A* \*/. ^ r( s, A6 z* ~ H- n* B. o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 s' p% v7 v8 nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* Q# M2 f4 Y4 _) k** Configure the McASP pins
) @- q$ P+ q: ]** Input - Frame Sync, Clock and Serializer Rx
/ \# ]3 {: m/ f) T [6 Y** Output - Serializer Tx is connected to the input of the codec
2 v2 _( Y# |8 _, i7 v, j*/7 d6 h0 c" J* }1 D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ t( b$ ~( \( y" A% ~5 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 w) k% J5 N3 C/ u7 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ S0 T" U! d) e- I& k& C. U || MCASP_PIN_ACLKX2 J/ C6 m+ e8 @5 s, ?
| MCASP_PIN_AHCLKX
9 v( C, f4 @# ^# P5 k. Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 H& l8 p8 a+ L4 h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 A" l( v9 f4 o# j| MCASP_TX_CLKFAIL
$ a* N' F( q+ Y9 j1 m/ r1 @, X% y| MCASP_TX_SYNCERROR, n" b6 V. R! V" t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ V4 Z0 ~2 H# v| MCASP_RX_CLKFAIL9 V! r Q% `/ Y) N. }9 y, {
| MCASP_RX_SYNCERROR - g8 @0 m- r* U: _1 `% z" ^
| MCASP_RX_OVERRUN);
6 S- `4 L' R2 G6 M9 `/ O, ]$ e0 K3 F} static void I2SDataTxRxActivate(void)
, w4 o1 \, T$ X, D$ L{
& K' } v/ R1 b/* Start the clocks */
" w7 S" B" t, W5 O6 G eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 X1 _; \/ M8 e# V% V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. m( [9 e' m4 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," B$ H# a: A+ T& ?; X
EDMA3_TRIG_MODE_EVENT);
& N: r6 _# \* F- ^+ \! fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + R" \8 Z; H$ p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 Q; K; c: G3 I+ e( y3 R* ]+ OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 M& O/ K3 \. |) W, C4 |$ nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ L0 f0 s! s) V" X9 Y- A o S( `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ R2 F/ y |/ I0 o. s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* G9 F. \* m3 x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; E" t" o i9 z, i ?9 o9 c
} ( ?/ O0 E0 J* R2 r3 c' H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % E! h7 t0 E$ Q7 L. T
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